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Connect a Display to a Trizeps
Applies to: Trizeps-IV, Trizeps IV WL, Trizeps-V.
See also: Display, BitmapBoot Tool.
Schematic
Typical connection of a Display
Signals
This is the signal-mapping, when using 8/16Bpp displays.
18Bpp is not supported in the current Windows CE drivers, because of it many disadavantages compared to the win of 2 extra display-lines. If needed LDD16 and LDD17 are mounting options on pins 150 and 152 of the Trizeps-module. If more display-lines for each color are availlable for a display, tie the LSB-bits together or connect them to ground. Usually displays also have additional control-lines for backlight and power. See BitmapBoot Tool on how to configure those options; i.e. backlight-PWM or power-enable GPIO's. Some smart-displays might also require special init-sequences using SPI or I2C. Contact Keith & Koep for more information on how to handle those.
| Signal-Name | SODIMM-Pin | Remark |
|---|---|---|
| LDD0 | 76 | blue[0] LSB |
| LDD1 | 70 | blue[1] |
| LDD2 | 60 | blue[2] |
| LDD3 | 58 | blue[3] |
| LDD4 | 78 | blue[4] MSB |
| LDD5 | 72 | green[0] LSB |
| LDD6 | 80 | green[1] |
| LDD7 | 46 | green[2] |
| LDD8 | 62 | green[3] |
| LDD9 | 48 | green[4] |
| LDD10 | 74 | green[5] MSB |
| LDD11 | 50 | red[0] LSB |
| LDD12 | 52 | red[1] |
| LDD13 | 54 | red[2] |
| LDD14 | 66 | red[3] |
| LDD15 | 64 | red[4] MSB |
| L_DEN | 44 | Data Enable for active-displays, Bias for passive displays. |
| L_PCLK | 56 | Pixel Clock |
| L_HSYNC | 68 | Horizontal Sync |
| L_VSYNC | 82 | Vertical Sync |
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